This invention relates generally to methods and circuit configurations for measuring signal propagation delays, and in particular for measuring signal propagation delays through integrated circuits.
Integrated circuits (ICs) are the cornerstone of myriad computational systems, such as personal computers and communications networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that guarantee superior speed performance. This leads IC manufacturers to carefully test the speed performance of their designs.
FIG. 1 depicts a conventional test configuration 100 for determining the signal propagation delay of a test circuit 110 in a conventional IC 115. A tester 120 includes an output lead 125 connected to an input pin 130 of IC 115. Tester 120 also includes an input line 135 connected to an output pin 140 of IC 115.
Tester 120 applies an input signal to input pin 130 and measures how long the signal takes to propagate through test circuit 110 to output pin 140. The resulting time period is the timing parameter for the path of interest. Such parameters are typically published in literature associated with particular ICs or used to model the speed performance of circuit designs that employ the path of interest.
Conventional test procedures are problematic for at least two reasons. First, many signal paths within a given IC cannot be measured directly, leading to some speculation as to their true timing characteristics. Second, testers have tolerances that can have a significant impact on some measurements, particularly when the signal propagation time of interest is short. For example, if the tester is accurate to one nanosecond and the propagation delay of interest is measured to be one nanosecond, the actual propagation delay might be any time between zero and two nanoseconds. In such a case the IC manufacturer would have to list the timing parameter as two nanoseconds, the worst-case scenario. If listed timing parameters are not worst-case values, some designs may fail. Thus, IC manufacturers tend to add relatively large margins of error, or xe2x80x9cguard bands,xe2x80x9d to ensure that their circuits will perform as advertised. Unfortunately, this means that those manufacturers will not be able to guarantee their full speed performance, which could cost them customers in an industry where speed performance is paramount.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks, or CLBs, that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that, by determining the states of various programming points, define how the CLBs, interconnections, and IOBs are configured.
Each programming point, CLB, interconnection line, and IOB introduces some delay into a signal path. The many potential combinations of these and other delay-inducing elements make timing predictions particularly difficult. FPGA designers use circuit models, called xe2x80x9cspeed files,xe2x80x9d that include delay values or resistance and capacitance values for the various delay-inducing elements that can be combined to form desired signal paths. These circuit models are then used to predict circuit timing for selected FPGA configurations.
Manufacturers of ICs, including FPGAs, would like to guarantee the highest speed timing specifications possible without causing FPGAs to fail to meet timing specifications. More accurate measurements of circuit timing allow IC manufacturers to use smaller guard bands to ensure correct device performance, and therefore to guarantee higher speed performance. There is therefore a need for a more accurate means of characterizing IC speed performance.
The present invention addresses the need for an accurate means of characterizing IC speed performance. The inventive circuit is particularly useful for testing programmable logic devices, which can be programmed to include a device for testing and a majority of the requisite test circuitry.
In accordance with the invention, a PLD is configured to implement a free-running oscillator within the elements of the PLD to be tested. That is, the PLD is programmed to form a loop through PLD elements to be tested. In one embodiment of the invention the oscillator includes synchronous components and oscillates at a frequency determined by the clock-to-out delay of those components. The oscillating frequency can thus be used to characterize synchronous components to provide data for accurately predicting the timing behavior of circuits that include those or similar components.
In accordance with the invention, a test circuit that includes one or more synchronous components is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The synchronous components propagate signals in response to one type of signal transition (e.g., a rising edge) on a clock input terminal. Each synchronous component is therefore equipped with a feedback element that resets the component a predetermined time after the component is clocked. The reset signal is delayed enough that subsequent components are clocked before the originating component resets.
The oscillator provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions may then be counted over a predetermined time period to establish the period of the oscillator, which may in turn be related to the clock-to-out delay of the synchronous component or components in the oscillator.
Signal paths often exhibit different propagation delays for falling and rising edges, due to imbalanced driver circuits, for example. The present invention addresses this problem by providing embodiments that measure the clock-to-out delays associated with both rising and falling edges. The worst-case delay associated with a given component can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.